The transition of silicon carbide manufacturing from 150mm to 200mm wafers is changing how SiC epitaxial wafers need to be specified, inspected and qualified.
For R&D applications, a customer may be able to work with a relatively simple specification covering wafer diameter, epitaxial thickness, doping concentration and surface roughness. For volume production, however, these parameters are no longer sufficient.
A 200mm SiC epitaxial wafer must deliver consistent material properties across a much larger usable area. Thickness uniformity, doping uniformity, basal plane dislocation behavior, surface defect distribution, wafer geometry and edge exclusion all influence downstream device yield.
More importantly, mass production requires consistency not only within one wafer, but also from wafer to wafer and from lot to lot.
For buyers qualifying 200mm SiC epi wafers, the key question is therefore no longer simply:
“Can the supplier grow a 200mm SiC epitaxial layer?”
The more important question is:
“Can the supplier repeatedly deliver the required electrical, structural and surface properties across the usable area of every wafer?”
This article explains the most important specifications for evaluating 200mm SiC epitaxial wafers for production applications.
Why 200mm SiC Epitaxy Is More Difficult Than 150mm
Moving from a 150mm wafer to a 200mm wafer increases the usable wafer area substantially, which creates an opportunity to process more devices per wafer.
However, larger diameter also makes epitaxial process control more difficult.
During SiC chemical vapor deposition, several conditions must remain stable across the entire wafer surface:
gas flow,
temperature,
precursor concentration,
dopant incorporation,
wafer rotation,
surface reaction rate,
and local growth conditions.
A small radial variation that is manageable on a 150mm wafer can become much more significant over a 200mm diameter.
This is why production qualification should focus on full-wafer uniformity rather than only nominal values measured near the wafer center.
1. Starting Substrate Quality Comes First
High-quality epitaxy cannot completely compensate for a poor underlying SiC substrate.
Before defining the epitaxial layer, buyers should establish the specification of the starting substrate.
For most conventional power-device applications, the substrate is typically an n-type 4H-SiC wafer with a defined off-axis orientation and an epi-ready Si-face surface.
Important substrate parameters include crystal polytype, conductivity type, orientation, off-axis angle, thickness, TTV, bow, warp, surface roughness and crystallographic defect density.
The relationship between substrate quality and epitaxy is especially important for basal plane dislocations, threading dislocations and other crystal defects.
If the substrate contains an unfavorable defect distribution, some of those defects can interact with the epitaxial layer and reduce the usable device area.
For 200mm qualification, substrate defect mapping should therefore be considered together with epitaxial defect inspection rather than treated as two completely independent quality-control steps.
2. Epilayer Thickness Must Be Defined as a Distribution
Nominal epitaxial thickness is one of the first parameters specified for a SiC epi wafer.
Depending on the target device, customers may require a relatively thin drift layer or a much thicker epitaxial structure.
However, for volume production, nominal thickness alone provides limited information.
Consider two 200mm wafers with the same average epilayer thickness.
The first wafer may show a relatively uniform radial profile.
The second may be thinner in the center and thicker near the edge.
Even if their average thickness is identical, the two wafers may produce very different device characteristics.
For this reason, an RFQ should distinguish between nominal epilayer thickness and within-wafer thickness uniformity.
Thickness mapping becomes particularly valuable on 200mm wafers because it allows engineers to identify radial trends, localized abnormalities and edge effects.
The measurement method should also be defined because results can vary depending on the technique, mapping pattern and calculation method.
FTIR is commonly used for SiC epitaxial thickness characterization.
For production qualification, customers should also evaluate wafer-to-wafer and run-to-run thickness repeatability.
A supplier that produces one excellent wafer but cannot maintain the same thickness distribution over multiple production runs is not yet demonstrating true mass-production capability.
3. Doping Concentration Directly Influences Electrical Performance
Doping concentration is another critical epitaxial parameter.
For a power-device drift region, the combination of epilayer thickness and doping concentration strongly influences breakdown voltage and specific on-resistance.
This means thickness and doping should not be evaluated independently.
If doping varies significantly across a 200mm wafer, electrical performance can vary from die to die even when epilayer thickness remains within specification.
Doping non-uniformity may originate from variations in gas distribution, temperature, dopant incorporation efficiency or local surface conditions during epitaxial growth.
As wafer diameter increases, controlling these conditions becomes more difficult.
A useful production specification should therefore define nominal doping concentration, allowable within-wafer variation and lot-to-lot repeatability.
It is also important to specify how uniformity is calculated.
For example, one supplier may describe uniformity using maximum and minimum values, while another may report standard deviation relative to the wafer mean.
Without a consistent calculation method, two quoted uniformity values may not be directly comparable.
For supplier qualification, the measurement method, number of measurement points, edge exclusion and uniformity equation should all be agreed in advance.
4. Why Full-Wafer Doping Maps Matter
A single average doping value cannot show where variation occurs.
A radial doping gradient, for example, may indicate a different epitaxial process issue from a localized high-doping region.
Full-wafer mapping can help reveal whether variation is associated with:
center-to-edge behavior,
gas-flow distribution,
temperature distribution,
wafer rotation,
reactor geometry,
or localized substrate conditions.
For device manufacturers, this information can also be correlated with electrical yield after fabrication.
As 200mm SiC enters more mature manufacturing environments, this type of material-to-device correlation will become increasingly important.
The objective is not merely to determine whether a wafer passes inspection.
The objective is to understand whether material variation is predictable and sufficiently stable for high-volume processing.
5. BPD Control Is a Key SiC Epitaxy Issue
Basal plane dislocations, commonly abbreviated as BPDs, are an important defect category in SiC materials.
BPDs may originate in the substrate and interact with the growing epitaxial layer.
During properly controlled epitaxial growth, some substrate BPDs can convert into threading edge dislocations rather than continuing through the epilayer as basal plane defects.
This BPD-to-TED conversion is therefore an important aspect of SiC epitaxy engineering.
Reducing BPD propagation is particularly important for device structures where bipolar current may occur.
BPD-related stacking-fault expansion can affect device stability and long-term electrical behavior.
For this reason, simply specifying substrate BPD density may not be sufficient.
A more complete material qualification can consider:
substrate BPD density,
BPD behavior after epitaxy,
BPD-to-TED conversion effectiveness,
remaining epi BPD distribution,
and the inspection method used to detect these defects.
For 200mm production, spatial distribution is again important.
Two wafers with the same total number of BPD-related defects may create different device yields if one wafer has defects concentrated in a particular radial region.
6. Surface Defects Must Be Classified, Not Just Counted
The surface of a SiC epitaxial wafer can contain several different defect types.
A total defect count alone may therefore be misleading.
Common epi-related surface defects can include triangular defects, carrot defects, pits, particles, step-bunching features, scratches and growth-related morphological abnormalities.
Different defects have different origins and different effects on device fabrication.
A particle-related defect may indicate contamination or reactor conditions.
A triangular defect may be associated with crystallographic or epitaxial growth behavior.
Scratches can originate from handling or the substrate surface.
Step bunching may indicate surface morphology or growth-condition issues.
Because these defect classes are not equivalent, buyers should avoid using only one specification such as:
“Total surface defects < X.”
A better qualification process defines relevant defect classes, detection thresholds, inspection area and acceptable density or count for each critical category.
Automated wafer inspection is particularly useful for 200mm material because manual inspection cannot reliably characterize the entire usable area with sufficient repeatability.
7. Surface Roughness Is Necessary but Not Sufficient
Atomic force microscopy is commonly used to evaluate nanoscale surface roughness.
A low Ra value is important for subsequent semiconductor fabrication, but an RFQ should not define surface quality using Ra alone.
The AFM scan size must also be specified.
A roughness result obtained from a very small scan area does not necessarily represent the complete wafer.
Furthermore, a wafer can show excellent AFM roughness while still containing localized scratches, particles, pits or epi defects.
Production surface qualification should therefore combine nanoscale roughness measurement with large-area defect inspection.
The objective is both microscopic smoothness and macroscopic defect control.
8. Edge Exclusion Can Change the Meaning of a Specification
Edge exclusion is one of the most easily overlooked parameters when comparing SiC epitaxial wafer quotations.
Epitaxial thickness, doping and defect performance usually become more difficult to control near the extreme wafer edge.
As a result, many specifications apply only to the usable area inside a defined edge exclusion.
This means that two suppliers can quote apparently similar uniformity numbers while actually evaluating different wafer areas.
For example, a result calculated after excluding a larger edge region may appear better than one measured closer to the wafer edge.
Therefore, every uniformity or defect specification should clearly define its corresponding edge exclusion.
This is particularly important for 200mm wafers because the customer wants to maximize usable die area.
A larger exclusion zone may improve reported material statistics but reduce the economically usable area of the wafer.
The correct edge exclusion is therefore a compromise between realistic epitaxial capability and device-fabrication requirements.
9. Edge Defects Become More Important at 200mm
Beyond measurement exclusion, the physical wafer edge itself requires careful control.
Possible edge-related issues include chipping, microcracks, contamination, polishing damage and abnormal epitaxial growth near the bevel.
These defects can create problems during automated handling or subsequent thermal processing.
Because 200mm SiC wafers have a larger diameter while remaining mechanically brittle, edge quality can influence both wafer breakage risk and downstream process stability.
For production sourcing, edge inspection should therefore be included in incoming quality control rather than treated as a cosmetic requirement.
10. TTV, Bow and Warp Still Matter After Epitaxy
Epitaxial specifications often focus heavily on electrical and crystallographic properties, but wafer geometry remains important.
The relevant parameters include total thickness variation, bow and warp.
These three terms describe different aspects of wafer geometry.
TTV evaluates thickness variation.
Bow describes the overall curvature of the wafer relative to a reference plane.
Warp represents the total deviation of the wafer median surface.
Excessive wafer deformation can interfere with automated handling, vacuum chucking, lithography focus, ion implantation and other fab processes.
For 200mm manufacturing, geometry requirements should be established according to the downstream process equipment.
An epi wafer may meet all material-quality requirements but still create manufacturing problems if its shape cannot be handled reliably by a production line.
11. Epitaxy Can Change Wafer Shape
The starting substrate may already meet strict bow and warp specifications before epitaxy.
However, the high-temperature epitaxial process can modify wafer stress and geometry.
This becomes particularly important when growing thick layers, multilayer structures or structures with significant doping differences.
Therefore, customers evaluating production epi wafers should distinguish between substrate geometry before epitaxy and final wafer geometry after epitaxy.
The final epi wafer is the material that downstream fabrication equipment will actually process.
Consequently, final-wafer TTV, bow and warp are normally more useful from the device-fabrication perspective.
12. Wafer-to-Wafer Repeatability Separates R&D from Mass Production
A technically impressive demonstration wafer does not prove mass-production readiness.
For volume manufacturing, repeatability is one of the most important acceptance criteria.
Suppose one wafer shows excellent thickness uniformity and doping uniformity.
If the following wafer has a substantially different distribution, the material is difficult to integrate into a stable semiconductor process.
Production qualification should therefore evaluate multiple wafers and multiple growth runs.
Engineers should examine whether the mean thickness, mean doping, radial profiles, surface defect levels and wafer geometry remain stable.
This is where statistical process control becomes increasingly important.
The objective is to demonstrate a controlled manufacturing window rather than a best-case result.
13. Lot-to-Lot Consistency Is Critical for Device Yield
After initial supplier qualification, lot-to-lot consistency becomes the next concern.
Power-device fabs typically optimize implantation, oxidation, metallization and device-design parameters around a known material window.
Large changes in epitaxial properties can therefore affect electrical distribution and yield.
For long-term sourcing, customers should monitor trends such as:
mean epilayer thickness,
thickness distribution,
mean doping concentration,
doping distribution,
critical surface defects,
BPD-related defects,
bow and warp,
and particle performance.
Trend charts can often provide more useful information than evaluating each wafer certificate independently.
A gradual process drift may remain inside individual acceptance limits while still indicating that the supplier’s manufacturing process is changing.
14. Measurement Methods Must Be Defined in the RFQ
A technical specification is meaningful only when the measurement method is clear.
For example, epilayer thickness may be measured using FTIR, while doping can be characterized using capacitance-voltage methods or other calibrated electrical techniques.
Surface roughness may be measured using AFM.
Surface defects may be evaluated using automated optical inspection systems.
Wafer geometry requires dedicated metrology equipment.
The RFQ should therefore specify not only the acceptance value but also, where important, the measurement method, mapping pattern, edge exclusion and reporting format.
This makes supplier comparison significantly more reliable.
15. Traceability Becomes More Important at Volume Scale
As SiC production moves toward higher volumes, traceability becomes increasingly valuable.
Each 200mm epi wafer should ideally be traceable through the major manufacturing stages.
This can include the crystal boule, substrate wafer ID, polishing lot, epitaxy run, inspection results and final shipping lot.
Good traceability helps engineers investigate correlations between material characteristics and device yield.
For example, if a device fab identifies an abnormal electrical distribution, wafer-level traceability can help determine whether the issue correlates with a specific crystal region, polishing batch or epitaxy run.
Without traceability, root-cause analysis becomes much more difficult.
16. What a Practical 200mm SiC Epi RFQ Should Define
A production-oriented RFQ should clearly separate the starting substrate specification from the epitaxial-layer specification.
The substrate section should define material type, crystal orientation, off-axis condition, thickness, geometry, surface condition and important crystal defects.
The epitaxy section should define layer structure, nominal thickness, doping concentration, thickness uniformity, doping uniformity, relevant crystal defects, surface-defect requirements and surface roughness.
Measurement conditions should then define mapping area, edge exclusion and inspection methodology.
Finally, production requirements should cover wafer identification, certificate-of-analysis content, wafer mapping, lot definition, traceability, packaging and required wafer-to-wafer consistency.
This format is much more useful than simply requesting:
“200mm 4H-SiC epitaxial wafer.”
17. Example Specification Structure
A practical specification sheet can be organized around the following items:
| Category | Parameter | Why It Matters |
|---|---|---|
| Substrate | 4H-SiC polytype | Crystal structure required for most power devices |
| Substrate | Conductivity type | Defines electrical substrate behavior |
| Substrate | Diameter | 200mm production compatibility |
| Substrate | Off-axis orientation | Influences step-flow epitaxy |
| Geometry | TTV | Controls thickness consistency |
| Geometry | Bow | Affects chucking and process compatibility |
| Geometry | Warp | Affects automated wafer processing |
| Epitaxy | Layer thickness | Influences device voltage design |
| Epitaxy | Thickness uniformity | Affects die-to-die electrical consistency |
| Epitaxy | Doping concentration | Influences breakdown voltage and resistance |
| Epitaxy | Doping uniformity | Controls electrical distribution across wafer |
| Crystal Defects | BPD | Important for material reliability |
| Crystal Defects | BPD-to-TED conversion | Indicates epitaxial defect control |
| Surface | Epi defect map | Determines usable device area |
| Surface | Roughness | Influences downstream wafer processing |
| Inspection | Edge exclusion | Defines actual measurement area |
| Production | Wafer-to-wafer variation | Indicates process repeatability |
| Production | Lot traceability | Supports yield analysis and quality control |
The exact numerical acceptance values should depend on the target device, voltage class, fab process and supplier capability.
Using one universal specification for every SiC device is generally inappropriate.
18. Supplier Qualification Should Focus on Data, Not Only Nominal Specifications
When comparing 200mm SiC epitaxial wafer suppliers, the specification sheet is only the starting point.
Production customers should request representative wafer maps and, where appropriate, data from multiple growth runs.
A strong qualification package should demonstrate consistent thickness distribution, doping distribution, defect mapping and wafer geometry.
This allows the customer to evaluate the process rather than a single wafer.
For new suppliers or new 200mm production lines, pilot lots can be particularly useful.
The customer can process several lots through the intended fab flow and correlate incoming material characteristics with final electrical yield.
This creates a data-driven acceptance window.
19. 200mm Mass Production Is Ultimately a Uniformity Problem
Increasing wafer diameter creates economic value only when the additional wafer area is usable.
A nominally 200mm wafer provides limited benefit if a large outer region has unstable doping, poor thickness uniformity or excessive surface defects.
Therefore, the central challenge of 200mm SiC epitaxy is not simply growing a larger layer.
It is achieving controlled electrical and structural properties over nearly the entire wafer.
This is why epilayer uniformity, doping control, edge exclusion and defect mapping should be considered together.
Improving only one parameter does not guarantee better device yield.
Conclusion
The transition to 200mm SiC epitaxial wafers represents an important manufacturing step for the power semiconductor industry, but wafer diameter alone is not an adequate measure of production maturity.
For mass production, buyers need to evaluate the complete epi-wafer system.
Epilayer thickness must remain uniform across the usable wafer area. Doping concentration must be tightly controlled. Basal plane dislocations and their behavior during epitaxy must be understood. Surface defects need to be classified and mapped. Edge exclusion must be clearly defined. TTV, bow and warp must remain compatible with production equipment.
Above all, these parameters must remain stable from wafer to wafer and lot to lot.
For device manufacturers qualifying 200mm SiC epitaxial wafers, the most valuable supplier is therefore not necessarily the one reporting the best single specification.
The more important capability is repeatable control of the complete material window required for high-yield semiconductor manufacturing.
As SiC manufacturing continues to scale toward 200mm production, detailed wafer mapping, traceability, statistical process control and supplier-to-fab data correlation will increasingly determine whether large-diameter SiC delivers its expected cost and yield advantages.