Découpage de plaquettes is a critical process in semiconductor, MEMS, optical and advanced packaging manufacturing. After wafer fabrication, the wafer must be separated into individual dies, chips, substrates or custom pieces. Although dicing may look like a simple cutting step, it directly affects yield, edge strength, dimensional accuracy and downstream assembly reliability.
Common dicing defects include edge chipping, micro-cracks, excessive kerf loss, rough sidewalls, particle contamination and poor edge quality. For fragile materials such as silicon, glass, sapphire, quartz and silicon carbide, defect control is especially important.
What Is Wafer Dicing?
Wafer dicing is the process of cutting a wafer into smaller units using a mechanical blade, laser, stealth dicing or other precision separation method. The best process depends on wafer material, thickness, diameter, device layout, edge quality requirement and production volume.
Common wafer dicing methods include:
- Diamond blade dicing
- Découpage laser
- Découpage furtif
- Scribing and breaking
- Wire saw cutting for thicker substrates
- CNC cutting for custom shapes
Each method has advantages and limitations. Blade dicing is widely used because it is mature and cost-effective, but it may cause chipping if parameters are not controlled well. Laser dicing can reduce mechanical stress, but heat-affected zones and surface changes must be considered.
Why Defect Control Matters
Dicing defects can reduce usable yield and create hidden reliability risks. Even small chips or cracks may expand during cleaning, bonding, packaging, thermal cycling or device operation.
Poor dicing quality may lead to:
- Lower die yield
- Cracks during handling
- Edge breakage
- Poor bonding or sealing
- Contamination par les particules
- Dimensional mismatch
- Reduced mechanical strength
- Higher inspection and rejection cost
For semiconductor buyers, it is important to define not only the final size, but also edge chip limits, kerf width, sidewall quality and inspection standards.
Chipping: The Most Common Dicing Defect
Chipping is one of the most common problems in wafer dicing. It usually appears along the top edge, bottom edge or sidewall of the cut. Chipping can be caused by excessive mechanical force, improper blade selection, unstable wafer support, poor tape adhesion or unsuitable cutting parameters.
Important factors that affect chipping include:
- Wafer material hardness and brittleness
- Épaisseur de la plaquette
- Blade grit size and bond type
- Blade exposure and wear condition
- Vitesse de rotation de la broche
- Vitesse d'alimentation
- Profondeur de coupe
- Cooling water flow
- Mounting tape performance
- Wafer flatness and bow
Hard and brittle materials such as sapphire, quartz, glass and SiC usually require more careful parameter control than standard silicon wafers.
How to Reduce Chipping
To reduce chipping, the dicing process must balance cutting speed, blade condition, cooling and wafer support.
Common control methods include:
- Selecting the correct diamond blade
- Reducing feed rate for brittle materials
- Optimizing spindle speed
- Using proper coolant flow
- Checking blade wear regularly
- Improving wafer mounting stability
- Using suitable dicing tape
- Controlling cut depth
- Adding protective coating if needed
- Performing trial cuts before production
For very thin wafers or high-value substrates, process validation before batch cutting is strongly recommended.
Kerf Loss and Why It Matters
Kerf loss refers to the material removed during the cutting process. In blade dicing, kerf width is mainly determined by blade thickness and cutting behavior. In laser dicing, kerf width depends on laser spot size, energy and material response.
Kerf loss affects:
- Die count per wafer
- Layout design
- Material utilization
- Final part size
- Cost per usable part
- Street width requirement
If the dicing street is too narrow for the selected process, chipping and yield loss may increase. If the street is too wide, valuable wafer area may be wasted. Buyers should confirm the required kerf width early during design and RFQ communication.
Edge Quality Requirements
Edge quality is not only about appearance. It affects strength, cleanliness and reliability. A smooth, controlled edge can reduce crack propagation and improve handling performance.
Typical edge quality items include:
- Top-side chip size
- Back-side chip size
- Rugosité des flancs
- Microfissures
- Edge collapse
- Burr-like residues or debris
- Contamination par les particules
- Dimensional consistency
- Die corner quality
For optical, MEMS and advanced packaging applications, edge quality may be more important than standard dimensional tolerance.
Material Differences in Dicing
Different wafer materials behave differently during dicing.
Silicon wafers are widely processed and usually easier to dice than many hard materials, but thin wafers can still crack or break.
Glass wafers are brittle and prone to edge chips, especially when thickness is low or support is insufficient.
Sapphire wafers are hard and require suitable diamond tooling and slower cutting conditions.
Plaques de SiC are very hard and can cause faster tool wear, making process control and blade selection important.
Quartz and fused silica wafers require careful cooling and edge control to reduce cracks and chipping.
Because of these differences, buyers should avoid using one general dicing tolerance for all materials.
Inspection Methods for Dicing Quality
Inspection should be matched to the application and quality requirement. For general parts, visual inspection and optical microscopy may be enough. For semiconductor or advanced packaging use, more detailed inspection may be required.
Parmi les méthodes d'inspection courantes, on peut citer :
- Optical microscope inspection
- Digital microscope measurement
- Edge chip size measurement
- Dimensional measurement
- Sidewall inspection
- Particle inspection
- Surface cleanliness check
- Sample photos before shipment
- Inspection report if required
For high-reliability applications, buyers may also request cross-section analysis, strength testing or more advanced defect inspection.
What Buyers Should Confirm Before Wafer Dicing
A clear RFQ helps reduce misunderstanding and improves the chance of stable quality. Buyers should provide:
- Matériau de la plaquette
- Diamètre de la plaquette
- Épaisseur de la plaquette
- Final die or part size
- Dicing method preference
- Street width
- Kerf width requirement
- Edge chip limit
- Surface protection requirement
- Quantité
- Drawing or layout file
- Cleanliness requirement
- Packaging requirement
- Inspection report requirement
If the buyer is not sure which dicing method is best, the supplier can review the material, thickness and drawing to recommend a practical process.
Balancing Quality, Cost and Yield
The strictest dicing requirement is not always the best choice. Very tight edge chip limits, narrow kerf requirements or special inspection standards may increase processing time and cost. However, loose requirements may cause yield loss during later assembly.
The best approach is to define critical requirements based on the real application. For example, a dummy wafer may allow different edge standards than a MEMS device wafer or optical glass substrate.
Conclusion
Wafer dicing defect control is essential for improving yield, reducing breakage and ensuring downstream process stability. Chipping, kerf loss and edge quality should be clearly defined before production, especially for brittle or high-value materials such as glass, sapphire, quartz and SiC.
A successful dicing project depends on proper blade or laser process selection, stable wafer mounting, optimized cutting parameters and suitable inspection standards. For custom wafer dicing, buyers should provide drawings, material details, thickness, edge chip limits and cleanliness requirements to support accurate quotation and reliable production.
FAQ
What is the most common wafer dicing defect?
Edge chipping is one of the most common defects, especially for brittle materials such as glass, sapphire, quartz and SiC.
What causes kerf loss during wafer dicing?
Kerf loss is caused by material removal during cutting. It depends on blade thickness, laser spot size, process parameters and material behavior.
How can chipping be reduced?
Chipping can be reduced by selecting the right blade, controlling feed rate and spindle speed, using proper coolant, improving wafer support and checking tool wear.
Is laser dicing always better than blade dicing?
Not always. Laser dicing can reduce mechanical stress, but thermal effects and material compatibility must be considered.
What information is needed for a wafer dicing quotation?
Material, wafer diameter, thickness, final size, street width, tolerance, edge chip limit, quantity and drawing are important for quotation.