SOI Wafer Thickness Guide: Device Layer, BOX Thickness, Handle Wafer and Selection for MEMS, RF and Silicon Photonics

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Silicon-on-insulator wafers are not defined by a single thickness.

An SOI wafer is a multilayer engineered substrate, and its performance depends on the relationship between three major layers:

  • Silicon device layer
  • Buried oxide layer, or BOX
  • Silicon handle wafer

Changing the thickness of any one of these layers can significantly affect device performance, mechanical behavior, thermal characteristics and fabrication compatibility.

This is why an SOI wafer for a MEMS pressure sensor may look very different from an SOI wafer used for an RF switch or a silicon photonics waveguide.

For engineers and purchasing teams, simply requesting:

“200mm SOI wafer”

is therefore not enough.

A useful SOI specification should define the device layer thickness, BOX thickness, handle wafer thickness and the tolerance or uniformity required for each critical layer.

This guide explains how these thickness parameters affect SOI wafer performance and how to select a suitable structure for MEMS, RF and silicon photonics applications.

What Is the Structure of an SOI Wafer?

A typical SOI wafer consists of three layers.

From top to bottom:

Device Layer
↓
Buried Oxide — BOX
↓
Handle Silicon Wafer

Each layer performs a different function.

The device layer is the crystalline silicon in which active devices, MEMS structures or optical waveguides are fabricated.

The BOX layer electrically and physically separates the device layer from the underlying silicon.

The handle wafer provides mechanical support and, depending on the application, may also influence electrical, RF, thermal or micromachining performance.

Commercial bonded SOI platforms can offer device layers from approximately 1 μm to more than 200 μm, BOX layers from roughly 0.3 μm to above 5 μm, and handle layers across several hundred micrometers depending on wafer diameter and design.

However, these are manufacturing capability ranges rather than recommended values for every application.

The correct thickness must be selected according to the device.

1. What Is the SOI Device Layer?

The device layer is the upper single-crystal silicon layer.

This is normally the most application-sensitive thickness parameter on an SOI wafer.

Depending on the process, the device layer may contain:

  • MEMS mechanical structures
  • transistors
  • أجهزة الترددات اللاسلكية
  • optical waveguides
  • resonators
  • microfluidic structures
  • sensing elements
  • power semiconductor structures

Its thickness can range from nanometers in some electronic and photonic platforms to more than 100 μm in structural MEMS devices.

That enormous range explains why the phrase “SOI thickness” is often too vague for purchasing.

Why Device Layer Thickness Matters

The device layer can directly determine:

  • mechanical stiffness
  • resonant frequency
  • membrane thickness
  • proof-mass geometry
  • optical mode confinement
  • transistor architecture
  • electrical characteristics
  • etch depth
  • process time
  • device sensitivity

For many SOI applications, device-layer thickness is not merely a wafer specification.

It is part of the actual device design.

Device Layer Thickness Uniformity

Nominal thickness alone is not enough.

Thickness uniformity across the wafer can be equally important.

Suppose a MEMS resonator is designed using a 20 μm silicon device layer.

If the actual silicon thickness changes significantly across the wafer, mechanical dimensions also change.

That can cause variation in:

  • resonant frequency
  • stiffness
  • mass
  • sensitivity

The same principle applies to silicon photonics.

Small variations in silicon waveguide geometry can change:

  • effective refractive index
  • phase
  • coupling behavior
  • resonant wavelength

This is why high-precision SOI platforms place strong emphasis on device-layer thickness uniformity. Commercial enhanced bonded SOI products can specify device-layer variation as tight as approximately ±0.1 μm for selected thicker SOI structures.

For nanometer-scale silicon photonics platforms, thickness control requirements are even more closely tied to the optical process.

2. What Is the BOX Layer?

BOX stands for Buried Oxide.

It is normally a silicon dioxide layer positioned between the top silicon device layer and the silicon handle wafer.

The BOX layer performs several functions depending on the application.

It can act as:

  • electrical insulation
  • an etch stop
  • an optical isolation layer
  • a sacrificial layer
  • a thermal barrier
  • part of a mechanical structure

Commercial bonded SOI wafers commonly use thermally grown oxide, with available BOX thicknesses extending from a few hundred nanometers to several micrometers.

Why BOX Thickness Matters

BOX thickness affects different applications in different ways.

For electronics, BOX reduces electrical interaction between the active device region and the underlying substrate.

For MEMS, BOX can serve as a highly useful etch-stop or sacrificial oxide.

For silicon photonics, the BOX helps optically separate the silicon waveguide from the silicon substrate.

Therefore, the correct BOX thickness depends strongly on what the engineer wants the oxide layer to do.

Thin BOX vs Thick BOX

A thinner BOX can be advantageous when:

  • strong thermal coupling to the substrate is desired
  • specific electrical architectures require thin isolation
  • back-gate interaction is part of the device design
  • the process requires only limited oxide separation

A thicker BOX can be advantageous when:

  • stronger electrical isolation is required
  • deeper oxide separation is useful
  • optical leakage into the substrate must be reduced
  • the BOX serves as a micromachining etch-stop or sacrificial structure

However, thicker is not automatically better.

Silicon dioxide has significantly lower thermal conductivity than crystalline silicon.

A thick BOX can therefore increase vertical thermal resistance.

For heat-generating devices, electrical or optical isolation must be balanced against thermal management.

3. What Is the Handle Wafer?

The handle wafer is the thick silicon layer underneath the BOX.

Its most obvious role is mechanical support.

Without the handle wafer, a thin SOI device layer could not be processed using standard wafer-handling equipment.

Typical handle wafers are hundreds of micrometers thick.

Commercial bonded SOI specifications can span approximately 300–950 μm depending on wafer size and application, while common 200mm configurations often fall within a narrower standard-processing range.

But handle thickness is only one parameter.

Engineers may also need to specify:

  • crystal orientation
  • resistivity
  • dopant
  • conductivity type
  • backside finish
  • thickness tolerance
  • flatness
  • TTV

Why Handle Wafer Properties Matter

In some applications, the handle wafer is mostly a mechanical carrier.

In others, it directly affects device performance.

على سبيل المثال:

RF-SOI

The electrical characteristics of the handle substrate can strongly influence RF losses and crosstalk.

MEMS

The handle wafer may be etched from the backside to create:

  • cavities
  • ports
  • diaphragms
  • through-wafer structures

Silicon Photonics

The handle mainly provides mechanical support, while the BOX separates optical structures from the underlying silicon.

This is why two SOI wafers with identical device-layer and BOX thicknesses can still behave differently if their handle substrates have different electrical properties.

Typical SOI Thickness Structure by Application

A simplified comparison looks like this:

التطبيقDevice LayerBOXHandle WaferMain Thickness Concern
MEMSμm to >100 μmUsually sub-μm to several μmHundreds of μmMechanical geometry
RF-SOITypically thin active siliconThin/moderate BOX depending on platformHigh-resistivity or engineered handleRF loss and isolation
Silicon PhotonicsOften hundreds of nmOften μm-scaleStandard mechanical supportOptical confinement
Power SOIThin to several μm depending on architectureApplication dependentSupporting substrateIsolation and breakdown
SensorsApplication dependentEtch-stop / isolationMechanical supportDimensional precision

These ranges are intentionally broad.

SOI should be specified from the actual device architecture rather than from an application name alone.

SOI Wafer Thickness for MEMS

MEMS is one of the most important applications for bonded SOI wafers.

SOI offers several advantages for MEMS fabrication because the device layer provides a well-controlled structural silicon thickness while the BOX can act as an etch-stop.

MEMS structures fabricated in SOI may include:

  • accelerometers
  • gyroscopes
  • pressure sensors
  • microphones
  • resonators
  • timing devices
  • micro-mirrors
  • ultrasonic transducers
  • microfluidic devices

Commercial MEMS-oriented bonded SOI platforms can provide device layers from around 1 μm to more than 200 μm.

This wide range exists because different MEMS devices require very different mechanical structures.

Thin Device Layers for MEMS

Relatively thin SOI device layers can be useful for:

  • flexible membranes
  • small resonators
  • low-mass mechanical structures
  • high-sensitivity pressure structures
  • specialized acoustic devices

A thinner silicon membrane is generally easier to deflect under pressure or force.

However, it also becomes more sensitive to:

  • thickness variation
  • residual stress
  • processing damage

Therefore, tight device-layer uniformity can become particularly important.

Thick Device Layers for MEMS

Thicker device layers may be selected for:

  • inertial sensors
  • large proof masses
  • high-aspect-ratio structures
  • strong mechanical structures
  • comb-drive devices
  • certain resonators

A thick SOI device layer also allows deep reactive ion etching to create nearly vertical silicon structures with well-controlled height.

For these applications, a difference of only a few micrometers in device-layer thickness can significantly affect device geometry.

BOX Selection for MEMS

The BOX layer often acts as an etch-stop during silicon micromachining.

For example, deep reactive ion etching can proceed through the device silicon until it reaches the buried oxide.

This allows the BOX to define the lower boundary of the silicon structure.

The oxide may subsequently remain in place or be selectively removed.

Therefore, BOX thickness may be selected according to:

  • electrical isolation requirements
  • etch-stop reliability
  • sacrificial oxide requirements
  • release process
  • cavity geometry

Commercial MEMS SOI products commonly use BOX layers in roughly the 0.3 μm to several-micrometer range, with 0.5–2 μm being common within some bonded SOI product families.

Handle Wafer Selection for MEMS

The handle wafer may be processed from the backside.

Therefore, engineers should consider:

  • handle thickness
  • orientation
  • backside polishing
  • resistivity
  • DRIE compatibility

If the device requires through-wafer etching, increasing handle thickness also increases the depth that must be etched.

A thicker handle provides greater mechanical rigidity but may increase backside processing time.

SOI Thickness for RF Applications

RF-SOI has become an important platform for RF switches and integrated front-end functions.

The design philosophy is different from MEMS.

In RF devices, the top silicon supports semiconductor devices while the substrate structure is engineered to reduce:

  • parasitic capacitance
  • substrate coupling
  • RF losses
  • harmonic distortion
  • crosstalk

High-resistivity SOI uses a high-resistivity silicon base, while enhanced RF-SOI structures may add a trap-rich layer beneath the BOX to further improve RF behavior.

Device Layer in RF-SOI

RF-SOI generally uses a much thinner active silicon layer than thick structural MEMS SOI.

The exact thickness is determined by:

  • transistor technology
  • foundry process
  • RF architecture
  • breakdown requirements
  • integration strategy

Therefore, engineers purchasing RF-SOI should not independently choose the top-silicon thickness without considering the target device process.

Unlike many R&D MEMS applications, RF-SOI is often part of a highly standardized semiconductor process platform.

BOX Thickness in RF-SOI

The BOX electrically isolates the active silicon from the handle substrate.

This helps reduce parasitic substrate interaction.

BOX thickness can influence:

  • capacitance
  • isolation
  • electric-field distribution
  • substrate coupling
  • thermal resistance

Again, thicker BOX does not automatically mean better RF performance.

The complete stack—including top silicon, BOX, trap-rich layer where applicable, and handle resistivity—must be engineered as a system.

High-Resistivity Handle Wafer

One of the most important RF-SOI specifications is often not thickness at all.

It is handle wafer resistivity.

High-resistivity silicon reduces RF substrate losses.

More advanced engineered RF-SOI substrates can introduce a trap-rich layer between the BOX and high-resistivity handle to suppress parasitic conduction and improve signal integrity.

Therefore, an RF-SOI RFQ should include electrical substrate requirements in addition to thickness.

SOI Wafer Thickness for Silicon Photonics

Silicon photonics has a very different thickness requirement from many MEMS applications.

Instead of using the silicon device layer primarily as a mechanical structure, silicon photonics uses the top silicon to form optical waveguides.

The thickness of this layer directly influences:

  • optical mode confinement
  • effective refractive index
  • waveguide dimensions
  • coupling
  • dispersion
  • bend performance

One widely used silicon photonics platform is based on approximately:

220 nm silicon device layer
+
2 μm BOX

For example, imec’s iSiPP200 platform uses 220 nm silicon on a 2000 nm BOX.

This is an important industry reference architecture, but it should not be interpreted as the only valid silicon photonics SOI thickness.

Why 220 nm Silicon Is Common in Silicon Photonics

At telecommunications wavelengths, a silicon layer around this thickness can support strongly confined silicon waveguides with compact dimensions.

This enables components such as:

  • strip waveguides
  • rib waveguides
  • ring resonators
  • Mach-Zehnder modulators
  • grating couplers
  • optical splitters

Because the optical mode is highly sensitive to geometry, thickness variation can change the optical characteristics.

Imec, for example, discusses optical coupling structures fabricated in a 220 nm crystalline silicon SOI layer.

This makes device-layer uniformity particularly important for photonics.

Why Silicon Photonics Uses a Thick BOX

The silicon handle wafer has a much higher refractive index than silicon dioxide.

If the BOX is too thin, part of the optical mode can interact with or leak toward the silicon substrate.

Increasing BOX thickness helps isolate the waveguide optically from the handle wafer.

This is why μm-scale BOX thickness is common in many silicon photonics platforms.

However, a thick oxide also increases thermal resistance.

That can matter for devices such as:

  • thermo-optic phase shifters
  • high-power photonic devices
  • integrated lasers
  • photonic-electronic co-packaged systems

Optical isolation and thermal management therefore need to be considered together.

Silicon Photonics Does Not Always Mean 220 nm

Other silicon thicknesses are used for specialized photonic architectures.

Depending on the device, engineers may select thicker silicon for:

  • low-loss waveguides
  • larger optical modes
  • edge couplers
  • sensors
  • nonlinear photonics
  • specialty integrated optics

Modern Photonics-SOI platforms are also used for high-speed optical transceivers and data-center interconnects, so wafer architecture is increasingly tied to foundry process design rather than a single universal thickness.

Therefore, purchasing should always begin with the photonic design platform.

Device Layer Thickness vs Device Layer Tolerance

This distinction is especially important when writing an SOI RFQ.

على سبيل المثال:

Device layer thickness: 10 μm

does not define how much the silicon thickness may vary.

The buyer should also specify:

Device layer thickness tolerance / uniformity

depending on the process.

For high-precision MEMS, resonators or photonics, thickness variation can affect performance even if average thickness is exactly correct.

BOX Thickness Uniformity

BOX thickness uniformity can also matter.

Possible impacts include:

  • electrical isolation variation
  • etch-stop behavior
  • membrane release
  • optical characteristics
  • capacitance variation

However, its importance differs between applications.

For a basic mechanical MEMS etch-stop, the BOX tolerance may be less critical than device silicon thickness.

For an electronic or optical device where the oxide forms part of the active field or mode structure, tighter control may be required.

Handle Wafer Thickness and Equipment Compatibility

The handle wafer must also be compatible with semiconductor processing equipment.

Important considerations include:

  • wafer diameter
  • total wafer thickness
  • robot handling
  • cassette or FOUP compatibility
  • chucking
  • lithography focus
  • backside processing

For standard semiconductor equipment, maintaining an appropriate total wafer thickness can simplify handling.

Extremely thin handle wafers may increase:

  • bow
  • warp
  • breakage risk
  • handling difficulty

Extremely thick handles may interfere with equipment designed around standard wafer thickness.

Total SOI Wafer Thickness

The approximate total SOI wafer thickness is:

Device Layer + BOX + Handle Wafer

However, because the BOX and top silicon can be very thin compared with the handle wafer, total thickness is often dominated by the handle.

For example, in a silicon photonics SOI wafer:

220 nm top Si
+ 2 μm BOX

  • hundreds of μm handle Si

the mechanical wafer thickness is effectively determined by the handle wafer.

In a thick-device-layer MEMS SOI wafer, the top silicon may contribute tens or hundreds of micrometers and therefore becomes much more important to total thickness.

BSOI vs Thin-Layer SOI

Manufacturing method also influences available thickness ranges.

Bonded SOI — BSOI

Bonded SOI is particularly suitable for relatively thick device layers.

Commercial bonded SOI can extend from approximately 1 μm to more than 200 μm, making it attractive for MEMS and other structures that require thick single-crystal silicon.

Thin SOI Platforms

Other processes are optimized for very thin and highly uniform top-silicon layers used for:

  • RF
  • FD-SOI
  • photonics
  • advanced electronics

Therefore, the target thickness should also guide selection of the SOI manufacturing technology.

How to Select SOI Thickness for MEMS

A practical MEMS selection process starts from the mechanical structure.

Ask:

How thick must the MEMS structure be?

This determines device-layer thickness.

Does the BOX act as an etch-stop?

If yes, select sufficient oxide for process reliability.

Will the handle wafer be backside etched?

If yes, handle thickness and orientation become important.

Is resonant frequency sensitive to silicon thickness?

If yes, prioritize device-layer thickness uniformity.

Does the device require a cavity?

A cavity SOI architecture may be more appropriate than standard planar SOI.

Cavity SOI platforms can incorporate buried cavities while maintaining controlled device, BOX and handle layers.

How to Select SOI Thickness for RF

For RF applications, start with the target semiconductor process rather than independently choosing wafer dimensions.

Key parameters include:

  • top silicon technology
  • BOX design
  • handle resistivity
  • trap-rich layer requirements
  • wafer diameter
  • thermal performance

For high-linearity applications, engineered substrates may provide advantages beyond conventional high-resistivity SOI.

The complete substrate stack should be qualified against:

  • insertion loss
  • harmonic distortion
  • crosstalk
  • linearity
  • device integration

How to Select SOI Thickness for Silicon Photonics

For silicon photonics, start with the optical design kit or foundry platform.

Confirm:

  • device silicon thickness
  • BOX thickness
  • wafer diameter
  • اتساق السماكة
  • surface roughness
  • crystal quality

If the design is built around a 220 nm platform, changing the device layer to 300 nm is not simply a wafer substitution.

Waveguide dimensions and optical behavior would need to be redesigned.

This is why silicon photonics SOI should generally be selected together with the fabrication process.

SOI Thickness Selection Summary

A useful simplified approach is:

MEMS

Prioritize:

Device-layer thickness and uniformity

because the top silicon often defines the mechanical structure.

RF

Prioritize:

Complete electrical substrate stack

including top silicon, BOX, handle resistivity and any engineered interface layer.

Silicon Photonics

Prioritize:

Precise device silicon + BOX architecture

because optical confinement depends directly on the layer dimensions.

Recommended SOI Wafer RFQ Information

When requesting a custom SOI wafer, provide as much of the following information as possible.

قطر الرقاقة

Examples:

  • 100mm
  • 150mm
  • 200mm
  • 300mm

Device Layer Thickness

Specify nominal thickness and tolerance.

Examples:

  • 220 nm
  • 2 μm
  • 10 ميكرومتر
  • 50 μm
  • 100 μm

Device Layer Properties

Specify:

  • crystal orientation
  • P-type / N-type
  • dopant
  • resistivity
  • surface finish

BOX Thickness

Provide:

  • target thickness
  • acceptable tolerance

Handle Wafer Thickness

Specify:

  • nominal thickness
  • tolerance

or request a standard thickness compatible with the wafer diameter.

Handle Wafer Electrical Properties

For applications such as RF, specify:

  • conductivity type
  • resistivity
  • engineered substrate requirements

Flatness Parameters

Depending on the process:

  • TTV
  • bow
  • warp
  • site flatness

Surface

Specify:

  • SSP
  • DSP
  • front-side polished
  • backside polished or etched

Edge / Terrace Requirements

Certain bonded SOI structures can include a peripheral terrace created by the bonding and thinning process.

If the process requires a terrace-free area or specific edge exclusion, this should be stated in advance.

التطبيق

Finally, indicate whether the wafer is intended for:

  • MEMS
  • RF
  • silicon photonics
  • sensor
  • جهاز الطاقة
  • البحث
  • bonding
  • another application

The application often allows the supplier to identify specifications that may otherwise be overlooked.

Common SOI Purchasing Mistakes

Mistake 1: Specifying Only Total Thickness

“725 μm SOI wafer” does not define the active SOI structure.

Device layer and BOX thickness must be specified separately.

Mistake 2: Ignoring Device Layer Uniformity

For precision MEMS and photonics, uniformity may matter as much as nominal thickness.

Mistake 3: Assuming Thicker BOX Is Always Better

Increasing BOX thickness may improve isolation but can also increase thermal resistance.

Mistake 4: Ignoring Handle Resistivity for RF

Two wafers with identical geometric thicknesses may behave differently at RF frequencies because of substrate electrical properties.

Mistake 5: Ordering Photonics SOI by Thickness Alone

A silicon photonics substrate must match the intended foundry and optical process.

Mistake 6: Over-Specifying Every Parameter

Tighter tolerances increase cost.

Specifications should reflect actual device requirements rather than automatically requesting the lowest possible TTV, roughness and thickness variation.

الخاتمة

SOI wafer thickness should always be treated as a three-layer engineering problem.

إن device layer determines the active silicon geometry.

إن BOX layer provides isolation, optical separation, etch-stop capability or sacrificial oxide.

إن handle wafer provides mechanical support and can also influence electrical, RF and micromachining performance.

For MEMS, device-layer thickness may range from only a few micrometers to more than 100 μm depending on the mechanical structure.

For RF-SOI, the entire electrical stack—including high-resistivity or engineered handle silicon—is critical.

For silicon photonics, nanometer-scale top-silicon control and μm-scale BOX isolation can directly determine optical performance.

There is therefore no universal “best SOI thickness.”

The correct SOI wafer is the one whose:

  • device layer
  • BOX thickness
  • handle wafer
  • اتساق السماكة
  • resistivity
  • flatness
  • surface condition

are matched to the device and fabrication process.

For engineers preparing an SOI RFQ, the most useful first question is not:

“What thickness SOI wafer do I need?”

It is:

“What function does each layer need to perform in my device?”

Once that is clear, the appropriate SOI thickness specification becomes much easier to define.