{"id":2627,"date":"2026-07-21T07:14:56","date_gmt":"2026-07-21T07:14:56","guid":{"rendered":"https:\/\/www.zmsh-semitech.com\/?p=2627"},"modified":"2026-07-21T07:18:49","modified_gmt":"2026-07-21T07:18:49","slug":"tgv-glass-wafer-supplier-guide","status":"publish","type":"post","link":"https:\/\/www.zmsh-semitech.com\/sv\/tgv-glass-wafer-supplier-guide\/","title":{"rendered":"TGV Glass Wafer Supplier Guide: Glass Type, Via Size, Metallization and RFQ"},"content":{"rendered":"<p>Through-glass via, commonly abbreviated as TGV, is an important interconnection technology used in advanced packaging, radio-frequency devices, MEMS, sensors, optical systems and wafer-level integration.<\/p>\n\n\n\n<p><a href=\"https:\/\/www.zmsh-semitech.com\/sv\/?s=TGV\"><mark style=\"background-color:rgba(0, 0, 0, 0);color:#fcb900\" class=\"has-inline-color\">TGV glass wafers<\/mark><\/a> contain vertical holes or conductive vias extending through the glass substrate. These structures can provide electrical connection, signal routing, thermal paths or alignment features while maintaining the electrical insulation, dimensional stability and optical properties of glass.<\/p>\n\n\n\n<p>However, purchasing TGV glass wafers requires more than specifying the wafer diameter and via size. The glass composition, wafer thickness, hole geometry, pitch, sidewall quality, metallization process and inspection standard all affect manufacturability, reliability and cost.<\/p>\n\n\n\n<p>This guide explains how to select a TGV glass wafer supplier and what technical information should be included in an RFQ.<\/p>\n\n\n\n<figure class=\"wp-block-image aligncenter size-large\"><img fetchpriority=\"high\" decoding=\"async\" width=\"1024\" height=\"768\" src=\"https:\/\/www.zmsh-semitech.com\/wp-content\/uploads\/2026\/07\/TGV-Glass-Wafer-Supplier-Guide-1024x768.png\" alt=\"\" class=\"wp-image-2628\" srcset=\"https:\/\/www.zmsh-semitech.com\/wp-content\/uploads\/2026\/07\/TGV-Glass-Wafer-Supplier-Guide-1024x768.png 1024w, https:\/\/www.zmsh-semitech.com\/wp-content\/uploads\/2026\/07\/TGV-Glass-Wafer-Supplier-Guide-300x225.png 300w, https:\/\/www.zmsh-semitech.com\/wp-content\/uploads\/2026\/07\/TGV-Glass-Wafer-Supplier-Guide-768x576.png 768w, https:\/\/www.zmsh-semitech.com\/wp-content\/uploads\/2026\/07\/TGV-Glass-Wafer-Supplier-Guide-16x12.png 16w, https:\/\/www.zmsh-semitech.com\/wp-content\/uploads\/2026\/07\/TGV-Glass-Wafer-Supplier-Guide-600x450.png 600w, https:\/\/www.zmsh-semitech.com\/wp-content\/uploads\/2026\/07\/TGV-Glass-Wafer-Supplier-Guide.png 1448w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\">What Is a TGV Glass Wafer?<\/h2>\n\n\n\n<p>A TGV glass wafer is a glass substrate containing holes that pass completely through the wafer thickness.<\/p>\n\n\n\n<p>Depending on the application, the vias may remain unfilled or may be coated, lined or completely filled with conductive metal.<\/p>\n\n\n\n<p>A typical TGV manufacturing process may include:<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li>Glass wafer preparation<\/li>\n\n\n\n<li>Via pattern definition<\/li>\n\n\n\n<li>Through-hole formation<\/li>\n\n\n\n<li>Cleaning and sidewall treatment<\/li>\n\n\n\n<li>Seed-layer deposition<\/li>\n\n\n\n<li>Metal plating or via filling<\/li>\n\n\n\n<li>Surface grinding or polishing<\/li>\n\n\n\n<li>Redistribution-layer processing<\/li>\n\n\n\n<li>Inspection and electrical testing<\/li>\n<\/ol>\n\n\n\n<p>TGV structures may be used for:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Vertical electrical interconnection<\/li>\n\n\n\n<li>Wafer-level packaging<\/li>\n\n\n\n<li>Fan-out packaging<\/li>\n\n\n\n<li>RF modules<\/li>\n\n\n\n<li>MEMS-f\u00f6rpackning<\/li>\n\n\n\n<li>Image sensors<\/li>\n\n\n\n<li>Optical sensors<\/li>\n\n\n\n<li>Interposers<\/li>\n\n\n\n<li>Mikrofluida enheter<\/li>\n\n\n\n<li>Hermetic package structures<\/li>\n\n\n\n<li>Antenna-in-package applications<\/li>\n<\/ul>\n\n\n\n<p>The final TGV specification must be designed around the electrical, mechanical, thermal and packaging requirements of the device.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Why Glass Is Used for Through-Via Substrates<\/h2>\n\n\n\n<p>Glass provides a combination of properties that can be useful in semiconductor and packaging applications.<\/p>\n\n\n\n<p>Potential advantages include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Electrical insulation<\/li>\n\n\n\n<li>Low electrical loss<\/li>\n\n\n\n<li>Adjustable coefficient of thermal expansion<\/li>\n\n\n\n<li>Good dimensional stability<\/li>\n\n\n\n<li>Smooth wafer surfaces<\/li>\n\n\n\n<li>Optical transparency<\/li>\n\n\n\n<li>Compatibility with fine-feature processing<\/li>\n\n\n\n<li>Availability in wafer formats<\/li>\n\n\n\n<li>Suitability for RF and high-frequency applications<\/li>\n\n\n\n<li>Potential for hermetic packaging structures<\/li>\n<\/ul>\n\n\n\n<p>The exact performance depends on the glass composition and manufacturing process.<\/p>\n\n\n\n<p>Not every glass wafer is suitable for TGV processing. The material must tolerate via formation, cleaning, metallization, thermal cycling and downstream packaging without excessive cracking, warpage or delamination.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">1. Select the Correct Glass Type<\/h2>\n\n\n\n<p>Glass composition is one of the first decisions in a TGV project.<\/p>\n\n\n\n<p>Common categories include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Borosilicate glass<\/li>\n\n\n\n<li>Aluminiumsilikatglas<\/li>\n\n\n\n<li>Fused silica<\/li>\n\n\n\n<li>Quartz glass<\/li>\n\n\n\n<li>Alkali-free glass<\/li>\n\n\n\n<li>Photosensitive glass<\/li>\n\n\n\n<li>Specialty packaging glass<\/li>\n<\/ul>\n\n\n\n<p>Each material has different electrical, thermal, optical and mechanical characteristics.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Borosilicate glass<\/h3>\n\n\n\n<p>Borosilicate glass is widely used for packaging, MEMS and sensor applications.<\/p>\n\n\n\n<p>Its potential advantages include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Good thermal stability<\/li>\n\n\n\n<li>Relatively low thermal expansion<\/li>\n\n\n\n<li>Compatibility with wafer-level processing<\/li>\n\n\n\n<li>Good chemical resistance<\/li>\n\n\n\n<li>Availability in multiple wafer sizes<\/li>\n\n\n\n<li>Suitability for anodic bonding in selected structures<\/li>\n<\/ul>\n\n\n\n<p>It may be considered for:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>MEMS-f\u00f6rpackning<\/li>\n\n\n\n<li>Trycksensorer<\/li>\n\n\n\n<li>Mikrofluida enheter<\/li>\n\n\n\n<li>Wafer-level caps<\/li>\n\n\n\n<li>Interposer structures<\/li>\n\n\n\n<li>General TGV development<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Aluminiumsilikatglas<\/h3>\n\n\n\n<p>Aluminosilicate glass can provide relatively high mechanical strength and thermal resistance.<\/p>\n\n\n\n<p>It may be selected for:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>High-density packaging<\/li>\n\n\n\n<li>Thin glass substrates<\/li>\n\n\n\n<li>Applications requiring improved mechanical durability<\/li>\n\n\n\n<li>Thermal-cycle-sensitive structures<\/li>\n\n\n\n<li>Fine-pitch TGV designs<\/li>\n<\/ul>\n\n\n\n<p>The exact composition should be reviewed because different aluminosilicate glasses can have significantly different electrical and thermal properties.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Fused silica<\/h3>\n\n\n\n<p>Fused silica offers high purity, excellent optical transmission and a very low coefficient of thermal expansion.<\/p>\n\n\n\n<p>It may be suitable for:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Optical packaging<\/li>\n\n\n\n<li>Fotonik<\/li>\n\n\n\n<li>High-temperature applications<\/li>\n\n\n\n<li>Precision sensor structures<\/li>\n\n\n\n<li>Low-expansion assemblies<\/li>\n\n\n\n<li>High-frequency applications<\/li>\n<\/ul>\n\n\n\n<p>However, via formation and metallization on fused silica may require specialized processing because of its material hardness and surface chemistry.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Alkali-free glass<\/h3>\n\n\n\n<p>Alkali-free glass is designed to reduce mobile-ion contamination.<\/p>\n\n\n\n<p>It may be considered for:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Semiconductor packaging<\/li>\n\n\n\n<li>Display-related processing<\/li>\n\n\n\n<li>Applications sensitive to sodium or potassium migration<\/li>\n\n\n\n<li>High-reliability electronic structures<\/li>\n<\/ul>\n\n\n\n<p>When alkali content is important, the RFQ should specify the required chemical composition or maximum permitted alkali concentration.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Photosensitive glass<\/h3>\n\n\n\n<p>Photosensitive glass can be patterned and selectively modified through exposure and thermal treatment.<\/p>\n\n\n\n<p>It may support:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Complex microstructures<\/li>\n\n\n\n<li>High-density holes<\/li>\n\n\n\n<li>Cavities and channels<\/li>\n\n\n\n<li>Integrated microfluidic features<\/li>\n\n\n\n<li>Precise three-dimensional structures<\/li>\n<\/ul>\n\n\n\n<p>The supplier should confirm whether the requested via profile, thickness and sidewall quality are compatible with the selected photosensitive process.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Glass Selection Parameters<\/h2>\n\n\n\n<p>The buyer should compare the following material properties:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Material parameter<\/th><th>Why it matters<\/th><\/tr><tr><td>Coefficient of thermal expansion<\/td><td>Influences stress during bonding and thermal cycling<\/td><\/tr><tr><td>Glass transition temperature<\/td><td>Affects high-temperature processing capability<\/td><\/tr><tr><td>Dielectric constant<\/td><td>Influences signal propagation and impedance<\/td><\/tr><tr><td>Dielectric loss<\/td><td>Important for RF and high-frequency devices<\/td><\/tr><tr><td>Electrical resistivity<\/td><td>Affects insulation performance<\/td><\/tr><tr><td>Thermal conductivity<\/td><td>Influences heat dissipation<\/td><\/tr><tr><td>Young\u2019s modulus<\/td><td>Affects stiffness and mechanical stress<\/td><\/tr><tr><td>Poisson\u2019s ratio<\/td><td>Used in mechanical modeling<\/td><\/tr><tr><td>Surface roughness<\/td><td>Affects bonding and metallization<\/td><\/tr><tr><td>Chemical durability<\/td><td>Important during cleaning and plating<\/td><\/tr><tr><td>Optical transmission<\/td><td>Required for optical and sensor applications<\/td><\/tr><tr><td>Alkali content<\/td><td>Important for contamination-sensitive devices<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>The glass type should be selected together with the packaging material, metal system and expected operating temperature.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">2. Define the Wafer Diameter and Thickness<\/h2>\n\n\n\n<p>Common TGV wafer diameters may include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>100 mm<\/li>\n\n\n\n<li>150 mm<\/li>\n\n\n\n<li>200 mm<\/li>\n\n\n\n<li>300 mm<\/li>\n\n\n\n<li>Custom round substrates<\/li>\n\n\n\n<li>Rectangular glass panels<\/li>\n<\/ul>\n\n\n\n<p>Wafer diameter affects:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Equipment compatibility<\/li>\n\n\n\n<li>Mask design<\/li>\n\n\n\n<li>Handling method<\/li>\n\n\n\n<li>Via count<\/li>\n\n\n\n<li>Production cost<\/li>\n\n\n\n<li>Inspection method<\/li>\n\n\n\n<li>Packaging and transportation<\/li>\n<\/ul>\n\n\n\n<p>Wafer thickness may range from thin interposer substrates to relatively thick glass packaging structures.<\/p>\n\n\n\n<p>The correct thickness depends on:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Required mechanical strength<\/li>\n\n\n\n<li>Via aspect ratio<\/li>\n\n\n\n<li>Package height<\/li>\n\n\n\n<li>Electrical design<\/li>\n\n\n\n<li>Handling method<\/li>\n\n\n\n<li>Bonding structure<\/li>\n\n\n\n<li>Grinding and polishing requirements<\/li>\n<\/ul>\n\n\n\n<p>Thin glass can reduce the required via depth and electrical path length, but it is more difficult to handle.<\/p>\n\n\n\n<p>Thick glass can provide greater rigidity but may increase:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Via formation time<\/li>\n\n\n\n<li>Via taper<\/li>\n\n\n\n<li>Metallization difficulty<\/li>\n\n\n\n<li>Filling time<\/li>\n\n\n\n<li>Restsp\u00e4nning<\/li>\n\n\n\n<li>Total processing cost<\/li>\n<\/ul>\n\n\n\n<p>The buyer should specify both the starting thickness and final thickness after grinding or polishing.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">3. Specify the Via Diameter Correctly<\/h2>\n\n\n\n<p>Via diameter is one of the most important TGV parameters.<\/p>\n\n\n\n<p>A supplier may request:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Top-side via diameter<\/li>\n\n\n\n<li>Bottom-side via diameter<\/li>\n\n\n\n<li>Minimum internal diameter<\/li>\n\n\n\n<li>Nominal via diameter<\/li>\n\n\n\n<li>Via diameter tolerance<\/li>\n<\/ul>\n\n\n\n<p>These values may be different when the hole has a tapered profile.<\/p>\n\n\n\n<p>For example, a via described only as 50 \u03bcm may be interpreted in several ways:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>50 \u03bcm at the top surface<\/li>\n\n\n\n<li>50 \u03bcm at the bottom surface<\/li>\n\n\n\n<li>50 \u03bcm average diameter<\/li>\n\n\n\n<li>50 \u03bcm minimum opening<\/li>\n\n\n\n<li>50 \u03bcm after metallization<\/li>\n\n\n\n<li>50 \u03bcm before metallization<\/li>\n<\/ul>\n\n\n\n<p>The RFQ must define where the diameter is measured and whether the dimension applies before or after metal deposition.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Typical Via Size Categories<\/h2>\n\n\n\n<p>TGV dimensions can vary widely according to the application.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td>Via category<\/td><td>General application<\/td><\/tr><tr><td>Large vias<\/td><td>Mechanical alignment, fluidic access or low-density interconnection<\/td><\/tr><tr><td>Medium vias<\/td><td>Standard packaging and sensor interconnection<\/td><\/tr><tr><td>Small vias<\/td><td>High-density electrical routing<\/td><\/tr><tr><td>Microvias<\/td><td>Fine-pitch interposers and advanced packaging<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>As the via diameter decreases, the process becomes more sensitive to:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Wafer thickness<\/li>\n\n\n\n<li>Aspect ratio<\/li>\n\n\n\n<li>Sidewall taper<\/li>\n\n\n\n<li>Debris removal<\/li>\n\n\n\n<li>Seed-layer continuity<\/li>\n\n\n\n<li>Plating uniformity<\/li>\n\n\n\n<li>Void formation<\/li>\n\n\n\n<li>Inspection capability<\/li>\n<\/ul>\n\n\n\n<p>Smaller vias do not automatically provide a better design. Via dimensions should be selected according to electrical requirements and manufacturing capability.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">4. Evaluate Via Aspect Ratio<\/h2>\n\n\n\n<p>The via aspect ratio is commonly defined as:<\/p>\n\n\n\n<p><strong>Aspect ratio = wafer thickness \u00f7 via diameter<\/strong><\/p>\n\n\n\n<p>For example, a 500 \u03bcm-thick wafer with a 100 \u03bcm via has an aspect ratio of 5:1.<\/p>\n\n\n\n<p>A higher aspect ratio may allow smaller vias in thicker wafers, but it also increases process difficulty.<\/p>\n\n\n\n<p>High-aspect-ratio vias can create challenges involving:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Hole formation<\/li>\n\n\n\n<li>Sidewall uniformity<\/li>\n\n\n\n<li>Debris removal<\/li>\n\n\n\n<li>Reng\u00f6ring<\/li>\n\n\n\n<li>Seed-layer coverage<\/li>\n\n\n\n<li>Metal plating<\/li>\n\n\n\n<li>Void control<\/li>\n\n\n\n<li>Inspection<\/li>\n\n\n\n<li>Electrical continuity<\/li>\n<\/ul>\n\n\n\n<p>Before finalizing the design, buyers should confirm the supplier\u2019s demonstrated capability for the specific combination of:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Glass type<\/li>\n\n\n\n<li>Wafer thickness<\/li>\n\n\n\n<li>Via diameter<\/li>\n\n\n\n<li>Via pitch<\/li>\n\n\n\n<li>Via profile<\/li>\n\n\n\n<li>Metallization method<\/li>\n<\/ul>\n\n\n\n<p>A supplier\u2019s minimum via diameter may only apply to thin glass or a limited via density. It should not be treated as a universal capability.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">5. Define the Via Profile<\/h2>\n\n\n\n<p>TGV holes may have different cross-sectional profiles.<\/p>\n\n\n\n<p>Common profiles include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Straight cylindrical vias<\/li>\n\n\n\n<li>Tapered vias<\/li>\n\n\n\n<li>Double-sided tapered vias<\/li>\n\n\n\n<li>Hourglass-shaped vias<\/li>\n\n\n\n<li>Conical vias<\/li>\n\n\n\n<li>Stepped vias<\/li>\n\n\n\n<li>Rounded-entry vias<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Straight via<\/h3>\n\n\n\n<p>A straight via has relatively consistent diameter through the wafer thickness.<\/p>\n\n\n\n<p>Potential benefits include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Predictable geometry<\/li>\n\n\n\n<li>Efficient use of substrate area<\/li>\n\n\n\n<li>Easier electrical modeling<\/li>\n\n\n\n<li>Suitable for dense layouts<\/li>\n<\/ul>\n\n\n\n<p>However, straight high-aspect-ratio holes may be more difficult to metallize uniformly.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Tapered via<\/h3>\n\n\n\n<p>A tapered via has different diameters at the top and bottom surfaces.<\/p>\n\n\n\n<p>Potential benefits include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Improved access for seed-layer deposition<\/li>\n\n\n\n<li>Easier plating<\/li>\n\n\n\n<li>Reduced risk of incomplete sidewall coverage<\/li>\n\n\n\n<li>Improved cleaning<\/li>\n<\/ul>\n\n\n\n<p>The disadvantages may include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Larger surface opening<\/li>\n\n\n\n<li>Reduced routing density<\/li>\n\n\n\n<li>Different electrical geometry<\/li>\n\n\n\n<li>More complex dimensional inspection<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Hourglass via<\/h3>\n\n\n\n<p>An hourglass profile may be created by processing the wafer from both sides.<\/p>\n\n\n\n<p>This can reduce the maximum drilling depth from either surface and may support thicker wafers.<\/p>\n\n\n\n<p>The central meeting point must be controlled to avoid:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Misalignment<\/li>\n\n\n\n<li>Restricted internal diameter<\/li>\n\n\n\n<li>Debris trapping<\/li>\n\n\n\n<li>Irregular metal filling<\/li>\n\n\n\n<li>Electrical discontinuity<\/li>\n<\/ul>\n\n\n\n<p>The drawing should show the complete via cross-section, not only the top opening.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">6. Determine the Via Pitch and Pattern<\/h2>\n\n\n\n<p>Via pitch is the center-to-center distance between adjacent vias.<\/p>\n\n\n\n<p>The minimum practical pitch depends on:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Via diameter<\/li>\n\n\n\n<li>Glass thickness<\/li>\n\n\n\n<li>Via formation method<\/li>\n\n\n\n<li>Heat-affected or modified region<\/li>\n\n\n\n<li>Required glass web thickness<\/li>\n\n\n\n<li>Crack risk<\/li>\n\n\n\n<li>Metallization design<\/li>\n\n\n\n<li>Redistribution-layer spacing<\/li>\n\n\n\n<li>Inspection capability<\/li>\n<\/ul>\n\n\n\n<p>The buyer should provide:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>X-direction pitch<\/li>\n\n\n\n<li>Y-direction pitch<\/li>\n\n\n\n<li>Staggered or aligned pattern<\/li>\n\n\n\n<li>Edge-to-via distance<\/li>\n\n\n\n<li>Via-to-via spacing<\/li>\n\n\n\n<li>Exclusion zones<\/li>\n\n\n\n<li>Alignment marks<\/li>\n\n\n\n<li>Total via count per wafer<\/li>\n<\/ul>\n\n\n\n<p>High via density can affect:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Wafer mechanical strength<\/li>\n\n\n\n<li>Krigssida<\/li>\n\n\n\n<li>Metal-plating uniformity<\/li>\n\n\n\n<li>Termisk p\u00e5frestning<\/li>\n\n\n\n<li>Processing time<\/li>\n\n\n\n<li>Yield<\/li>\n\n\n\n<li>Unit price<\/li>\n<\/ul>\n\n\n\n<p>A small test array should be produced before moving to a full-wafer, high-density design.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">7. Choose the Via Formation Method<\/h2>\n\n\n\n<p>Several processes can be used to create through-glass vias.<\/p>\n\n\n\n<p>The appropriate method depends on:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Glass composition<\/li>\n\n\n\n<li>Wafer thickness<\/li>\n\n\n\n<li>Via diameter<\/li>\n\n\n\n<li>Via density<\/li>\n\n\n\n<li>Sidewall-quality requirement<\/li>\n\n\n\n<li>Taper requirement<\/li>\n\n\n\n<li>Production volume<\/li>\n\n\n\n<li>Cost target<\/li>\n<\/ul>\n\n\n\n<p>Possible methods include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Laser-based processing<\/li>\n\n\n\n<li>Laser modification followed by chemical etching<\/li>\n\n\n\n<li>Mechanical drilling<\/li>\n\n\n\n<li>Ultrasonic machining<\/li>\n\n\n\n<li>Abrasive processing<\/li>\n\n\n\n<li>Plasma-assisted processing<\/li>\n\n\n\n<li>Photolithographic processing of photosensitive glass<\/li>\n\n\n\n<li>Combined processes<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Laser-based via formation<\/h3>\n\n\n\n<p>Laser processing can provide flexible patterning without physical masks.<\/p>\n\n\n\n<p>Potential advantages include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Programmable via locations<\/li>\n\n\n\n<li>Fast design changes<\/li>\n\n\n\n<li>Compatibility with multiple hole shapes<\/li>\n\n\n\n<li>Suitable for prototype and production work<\/li>\n<\/ul>\n\n\n\n<p>Potential concerns include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Heat-affected zones<\/li>\n\n\n\n<li>Mikrosprickor<\/li>\n\n\n\n<li>Recast material<\/li>\n\n\n\n<li>Sidewall roughness<\/li>\n\n\n\n<li>Taper<\/li>\n\n\n\n<li>Debris<\/li>\n\n\n\n<li>Restsp\u00e4nning<\/li>\n<\/ul>\n\n\n\n<p>The final result depends on the glass type, laser parameters and post-processing.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Laser modification and etching<\/h3>\n\n\n\n<p>In this process, selected regions of the glass are modified before chemical removal.<\/p>\n\n\n\n<p>Potential advantages may include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Fine features<\/li>\n\n\n\n<li>Reduced mechanical damage<\/li>\n\n\n\n<li>High-density patterns<\/li>\n\n\n\n<li>Controlled via profiles<\/li>\n<\/ul>\n\n\n\n<p>Important considerations include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Material compatibility<\/li>\n\n\n\n<li>Etch selectivity<\/li>\n\n\n\n<li>Sidewall roughness<\/li>\n\n\n\n<li>Process uniformity<\/li>\n\n\n\n<li>Cleaning requirements<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Mechanical or abrasive processing<\/h3>\n\n\n\n<p>Mechanical methods may be suitable for larger holes or lower-density designs.<\/p>\n\n\n\n<p>They may offer:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Straightforward processing<\/li>\n\n\n\n<li>Good control for larger features<\/li>\n\n\n\n<li>Suitability for thick substrates<\/li>\n<\/ul>\n\n\n\n<p>However, mechanical stress and edge chipping must be controlled.<\/p>\n\n\n\n<p>The buyer should focus on the finished-hole specification rather than requiring a particular manufacturing method unless the process itself is critical to product qualification.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">8. Define Sidewall Quality Requirements<\/h2>\n\n\n\n<p>Via sidewall quality affects metallization, reliability and electrical continuity.<\/p>\n\n\n\n<p>Important inspection items include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Sidewall roughness<\/li>\n\n\n\n<li>Mikrosprickor<\/li>\n\n\n\n<li>Chipping<\/li>\n\n\n\n<li>Debris<\/li>\n\n\n\n<li>Recast material<\/li>\n\n\n\n<li>Heat-affected region<\/li>\n\n\n\n<li>Surface contamination<\/li>\n\n\n\n<li>Internal constriction<\/li>\n\n\n\n<li>Irregular taper<\/li>\n\n\n\n<li>Glass damage around the via opening<\/li>\n<\/ul>\n\n\n\n<p>A rough sidewall may improve mechanical adhesion in some structures but can also create:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Discontinuous seed layers<\/li>\n\n\n\n<li>Current-density concentration<\/li>\n\n\n\n<li>Plating voids<\/li>\n\n\n\n<li>Increased conductor resistance<\/li>\n\n\n\n<li>Reliability risks<\/li>\n<\/ul>\n\n\n\n<p>The RFQ should define the acceptable inspection method and defect limit.<\/p>\n\n\n\n<p>Possible methods include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Optical microscopy<\/li>\n\n\n\n<li>Cross-sectional microscopy<\/li>\n\n\n\n<li>Confocal measurement<\/li>\n\n\n\n<li>Scanning electron microscopy<\/li>\n\n\n\n<li>X-ray inspection<\/li>\n\n\n\n<li>Surface profilometry<\/li>\n\n\n\n<li>Three-dimensional optical measurement<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">9. Select the Metallization Structure<\/h2>\n\n\n\n<p>TGV metallization may involve coating the via sidewall, partially filling the via or completely filling the via with conductive material.<\/p>\n\n\n\n<p>Common structures include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Sidewall metal lining<\/li>\n\n\n\n<li>Conformal metal coating<\/li>\n\n\n\n<li>Partial metal fill<\/li>\n\n\n\n<li>Complete copper fill<\/li>\n\n\n\n<li>Conductive paste fill<\/li>\n\n\n\n<li>Metal-filled via with redistribution layers<\/li>\n\n\n\n<li>Metal caps on both wafer surfaces<\/li>\n<\/ul>\n\n\n\n<p>The correct structure depends on:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Required electrical resistance<\/li>\n\n\n\n<li>Current-carrying capability<\/li>\n\n\n\n<li>Signal frequency<\/li>\n\n\n\n<li>Thermal requirements<\/li>\n\n\n\n<li>Mechanical reliability<\/li>\n\n\n\n<li>Package thickness<\/li>\n\n\n\n<li>Surface-planarity requirement<\/li>\n\n\n\n<li>Downstream bonding process<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">10. Understand the Metallization Process<\/h2>\n\n\n\n<p>A typical metallization process may include:<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li>Via cleaning<\/li>\n\n\n\n<li>Surface activation<\/li>\n\n\n\n<li>Adhesion-layer deposition<\/li>\n\n\n\n<li>Seed-layer deposition<\/li>\n\n\n\n<li>Electroplating or electroless plating<\/li>\n\n\n\n<li>Via filling or sidewall coating<\/li>\n\n\n\n<li>Surface metal removal<\/li>\n\n\n\n<li>Grinding or polishing<\/li>\n\n\n\n<li>Gl\u00f6dgning<\/li>\n\n\n\n<li>Redistribution-layer formation<\/li>\n\n\n\n<li>Elektriska provningar<\/li>\n<\/ol>\n\n\n\n<p>The process must produce continuous metal coverage through the complete via.<\/p>\n\n\n\n<p>Potential metallization defects include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Seed-layer discontinuity<\/li>\n\n\n\n<li>Plating voids<\/li>\n\n\n\n<li>Seams<\/li>\n\n\n\n<li>Copper overburden<\/li>\n\n\n\n<li>Surface pits<\/li>\n\n\n\n<li>Via blockage<\/li>\n\n\n\n<li>Poor adhesion<\/li>\n\n\n\n<li>Metal delamination<\/li>\n\n\n\n<li>Cracks caused by thermal stress<\/li>\n\n\n\n<li>Non-uniform resistance<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">11. Choose the Metal System<\/h2>\n\n\n\n<p>Copper is commonly considered for conductive TGV structures because of its electrical and thermal conductivity.<\/p>\n\n\n\n<p>Other metals or layers may also be used depending on the design.<\/p>\n\n\n\n<p>Possible materials include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Copper<\/li>\n\n\n\n<li>Titanium<\/li>\n\n\n\n<li>Chromium<\/li>\n\n\n\n<li>Nickel<\/li>\n\n\n\n<li>Gold<\/li>\n\n\n\n<li>Silver<\/li>\n\n\n\n<li>Tungsten<\/li>\n\n\n\n<li>Conductive paste<\/li>\n\n\n\n<li>Multi-layer metal stacks<\/li>\n<\/ul>\n\n\n\n<p>A typical metal stack may include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Adhesion layer<\/li>\n\n\n\n<li>Barrier layer<\/li>\n\n\n\n<li>Seed layer<\/li>\n\n\n\n<li>Plated conductor<\/li>\n\n\n\n<li>Surface-finish layer<\/li>\n<\/ul>\n\n\n\n<p>The buyer should specify:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Required conductor material<\/li>\n\n\n\n<li>Adhesion-layer material<\/li>\n\n\n\n<li>Barrier-layer requirement<\/li>\n\n\n\n<li>Final surface finish<\/li>\n\n\n\n<li>Minimum metal thickness<\/li>\n\n\n\n<li>Maximum resistance<\/li>\n\n\n\n<li>Bonding compatibility<\/li>\n\n\n\n<li>Corrosion-resistance requirement<\/li>\n<\/ul>\n\n\n\n<p>The supplier should also understand the downstream process, such as:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Wire bonding<\/li>\n\n\n\n<li>Flip-chip bonding<\/li>\n\n\n\n<li>Soldering<\/li>\n\n\n\n<li>Thermocompression bonding<\/li>\n\n\n\n<li>Conductive adhesive bonding<\/li>\n\n\n\n<li>Redistribution-layer formation<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">12. Sidewall Coating vs Full Via Filling<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Sidewall-coated TGV<\/h3>\n\n\n\n<p>In a sidewall-coated structure, metal covers the internal wall of the via while the center remains open.<\/p>\n\n\n\n<p>Potential advantages include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Lower metal volume<\/li>\n\n\n\n<li>Shorter plating time<\/li>\n\n\n\n<li>Reduced metal stress<\/li>\n\n\n\n<li>Lower processing cost<\/li>\n\n\n\n<li>Possible use as an open channel<\/li>\n<\/ul>\n\n\n\n<p>Potential limitations include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Higher electrical resistance than a fully filled via<\/li>\n\n\n\n<li>Greater sensitivity to coating discontinuity<\/li>\n\n\n\n<li>More difficult electrical inspection<\/li>\n\n\n\n<li>Limited current-carrying capability<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Fully filled TGV<\/h3>\n\n\n\n<p>A fully filled via contains conductive material across most or all of its cross-section.<\/p>\n\n\n\n<p>Potential advantages include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Lower electrical resistance<\/li>\n\n\n\n<li>Higher current capacity<\/li>\n\n\n\n<li>Better thermal conduction<\/li>\n\n\n\n<li>Potentially improved surface integration<\/li>\n<\/ul>\n\n\n\n<p>Potential challenges include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Longer plating time<\/li>\n\n\n\n<li>Void formation<\/li>\n\n\n\n<li>Internal seams<\/li>\n\n\n\n<li>Greater thermal-mechanical stress<\/li>\n\n\n\n<li>Surface overburden<\/li>\n\n\n\n<li>More complex grinding and polishing<\/li>\n<\/ul>\n\n\n\n<p>The buyer should define whether the requirement is:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Conformal coating<\/li>\n\n\n\n<li>Minimum wall thickness<\/li>\n\n\n\n<li>Partial fill percentage<\/li>\n\n\n\n<li>Void-free fill<\/li>\n\n\n\n<li>Complete metal fill<\/li>\n\n\n\n<li>Planarized metal surface<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">13. Control Copper-to-Glass Thermal Stress<\/h2>\n\n\n\n<p>Glass and copper expand at different rates during temperature changes.<\/p>\n\n\n\n<p>This mismatch can create stress around the via and may lead to:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Glass cracking<\/li>\n\n\n\n<li>Copper protrusion<\/li>\n\n\n\n<li>Metal delamination<\/li>\n\n\n\n<li>Interface separation<\/li>\n\n\n\n<li>Wafer warpage<\/li>\n\n\n\n<li>Reliability failure during thermal cycling<\/li>\n<\/ul>\n\n\n\n<p>Stress depends on:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Glass coefficient of thermal expansion<\/li>\n\n\n\n<li>Via diameter<\/li>\n\n\n\n<li>Via pitch<\/li>\n\n\n\n<li>Wafer thickness<\/li>\n\n\n\n<li>Copper volume<\/li>\n\n\n\n<li>Annealing conditions<\/li>\n\n\n\n<li>Operating-temperature range<\/li>\n\n\n\n<li>Redistribution-layer design<\/li>\n<\/ul>\n\n\n\n<p>The supplier should evaluate the complete material stack rather than considering the glass and metal independently.<\/p>\n\n\n\n<p>For high-reliability applications, thermal cycling and cross-sectional analysis may be required.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">14. Specify Surface Metallization and Redistribution Layers<\/h2>\n\n\n\n<p>Some projects require metal only inside the vias. Others require patterned metal lines on one or both wafer surfaces.<\/p>\n\n\n\n<p>Possible surface structures include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Metal pads<\/li>\n\n\n\n<li>Redistribution layers<\/li>\n\n\n\n<li>Ground planes<\/li>\n\n\n\n<li>Antenna structures<\/li>\n\n\n\n<li>Bonding rings<\/li>\n\n\n\n<li>Solderable pads<\/li>\n\n\n\n<li>Wire-bond pads<\/li>\n\n\n\n<li>Electroplated bumps<\/li>\n<\/ul>\n\n\n\n<p>The RFQ should specify:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Top-side metal pattern<\/li>\n\n\n\n<li>Bottom-side metal pattern<\/li>\n\n\n\n<li>Metal thickness<\/li>\n\n\n\n<li>Line width<\/li>\n\n\n\n<li>Line spacing<\/li>\n\n\n\n<li>Pad dimensions<\/li>\n\n\n\n<li>Surface finish<\/li>\n\n\n\n<li>Alignment tolerance between vias and pads<\/li>\n\n\n\n<li>Passivation requirement<\/li>\n\n\n\n<li>Bonding method<\/li>\n<\/ul>\n\n\n\n<p>A drawing should identify whether the supplier is responsible for:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>TGV hole formation only<\/li>\n\n\n\n<li>Hole formation and seed layer<\/li>\n\n\n\n<li>Hole formation and metal filling<\/li>\n\n\n\n<li>Complete TGV plus redistribution layers<\/li>\n\n\n\n<li>Final wafer-level interposer fabrication<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">15. Define Wafer Flatness, Bow and Warp<\/h2>\n\n\n\n<p>TGV processing and metal deposition can change wafer geometry.<\/p>\n\n\n\n<p>Important dimensional parameters include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Total tjockleksvariation<\/li>\n\n\n\n<li>B\u00e5ge<\/li>\n\n\n\n<li>Varp<\/li>\n\n\n\n<li>Local flatness<\/li>\n\n\n\n<li>Edge exclusion<\/li>\n\n\n\n<li>Surface roughness<\/li>\n\n\n\n<li>Parallelism<\/li>\n<\/ul>\n\n\n\n<p>Flatness becomes especially important for:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Litografi<\/li>\n\n\n\n<li>Wafer bonding<\/li>\n\n\n\n<li>Temporary bonding<\/li>\n\n\n\n<li>Redistribution-layer processing<\/li>\n\n\n\n<li>Slipning<\/li>\n\n\n\n<li>Inspection<\/li>\n\n\n\n<li>Automated wafer handling<\/li>\n<\/ul>\n\n\n\n<p>High via density and thick copper structures can increase wafer stress.<\/p>\n\n\n\n<p>The buyer should specify whether bow and warp limits apply:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Before via processing<\/li>\n\n\n\n<li>After via formation<\/li>\n\n\n\n<li>After metallization<\/li>\n\n\n\n<li>After thermal treatment<\/li>\n\n\n\n<li>At final delivery<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">16. Establish Inspection Requirements<\/h2>\n\n\n\n<p>A complete TGV inspection plan may include several levels.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Incoming glass inspection<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Wafer diameter<\/li>\n\n\n\n<li>Tjocklek<\/li>\n\n\n\n<li>Total tjockleksvariation<\/li>\n\n\n\n<li>Bow and warp<\/li>\n\n\n\n<li>Surface roughness<\/li>\n\n\n\n<li>Edge condition<\/li>\n\n\n\n<li>Scratch and defect inspection<\/li>\n\n\n\n<li>Material certification<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Via inspection<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Via diameter<\/li>\n\n\n\n<li>Top and bottom opening<\/li>\n\n\n\n<li>Taper angle<\/li>\n\n\n\n<li>Via pitch<\/li>\n\n\n\n<li>Position accuracy<\/li>\n\n\n\n<li>Sidewall quality<\/li>\n\n\n\n<li>Chipping<\/li>\n\n\n\n<li>Crack inspection<\/li>\n\n\n\n<li>Blocked-via inspection<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Metallization inspection<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Metal thickness<\/li>\n\n\n\n<li>Seed-layer continuity<\/li>\n\n\n\n<li>Void inspection<\/li>\n\n\n\n<li>Fill percentage<\/li>\n\n\n\n<li>Surface overburden<\/li>\n\n\n\n<li>Adhesion<\/li>\n\n\n\n<li>Electrical resistance<\/li>\n\n\n\n<li>Isolation resistance<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Final wafer inspection<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Wafer thickness<\/li>\n\n\n\n<li>Planhet<\/li>\n\n\n\n<li>Bow and warp<\/li>\n\n\n\n<li>Surface roughness<\/li>\n\n\n\n<li>Pad dimensions<\/li>\n\n\n\n<li>Redistribution-layer alignment<\/li>\n\n\n\n<li>Visual defects<\/li>\n\n\n\n<li>Wafer map<\/li>\n\n\n\n<li>Packaging condition<\/li>\n<\/ul>\n\n\n\n<p>The inspection standard should be agreed upon before production begins.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">17. Electrical Testing Requirements<\/h2>\n\n\n\n<p>Depending on the application, electrical testing may include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Continuity testing<\/li>\n\n\n\n<li>Via resistance<\/li>\n\n\n\n<li>Insulation resistance<\/li>\n\n\n\n<li>Leakage current<\/li>\n\n\n\n<li>Open-circuit detection<\/li>\n\n\n\n<li>Short-circuit detection<\/li>\n\n\n\n<li>Daisy-chain testing<\/li>\n\n\n\n<li>High-frequency characterization<\/li>\n\n\n\n<li>Current-carrying test<\/li>\n<\/ul>\n\n\n\n<p>The buyer should specify:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Maximum resistance per via<\/li>\n\n\n\n<li>Maximum resistance variation<\/li>\n\n\n\n<li>Minimum insulation resistance<\/li>\n\n\n\n<li>Test voltage<\/li>\n\n\n\n<li>Test current<\/li>\n\n\n\n<li>Sampling level<\/li>\n\n\n\n<li>Wafer-map format<\/li>\n\n\n\n<li>Pass\/fail criteria<\/li>\n<\/ul>\n\n\n\n<p>Electrical testing becomes more important after complete metallization or redistribution-layer processing.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">18. Reliability Testing<\/h2>\n\n\n\n<p>High-reliability TGV structures may require:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Termisk cykling<\/li>\n\n\n\n<li>High-temperature storage<\/li>\n\n\n\n<li>Temperature-humidity testing<\/li>\n\n\n\n<li>Pressure-cooker testing<\/li>\n\n\n\n<li>Metal-adhesion testing<\/li>\n\n\n\n<li>Bond-strength testing<\/li>\n\n\n\n<li>Mechanical bending<\/li>\n\n\n\n<li>Wafer-level warpage measurement<\/li>\n\n\n\n<li>Cross-sectional inspection<\/li>\n\n\n\n<li>Current-stress testing<\/li>\n<\/ul>\n\n\n\n<p>The required reliability plan depends on the final application.<\/p>\n\n\n\n<p>An RF device, optical sensor and automotive package may require different qualification conditions.<\/p>\n\n\n\n<p>The supplier should understand:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Operating-temperature range<\/li>\n\n\n\n<li>Storage-temperature range<\/li>\n\n\n\n<li>Package assembly process<\/li>\n\n\n\n<li>Expected service life<\/li>\n\n\n\n<li>Environmental exposure<\/li>\n\n\n\n<li>Required qualification standard<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">19. Prototype Development Before Volume Production<\/h2>\n\n\n\n<p>TGV projects should normally begin with a design review and prototype stage.<\/p>\n\n\n\n<p>A practical development sequence may include:<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li>Material selection<\/li>\n\n\n\n<li>Via-layout review<\/li>\n\n\n\n<li>Process-feasibility evaluation<\/li>\n\n\n\n<li>Test-coupon production<\/li>\n\n\n\n<li>Small-array fabrication<\/li>\n\n\n\n<li>Metallization trial<\/li>\n\n\n\n<li>Cross-sectional inspection<\/li>\n\n\n\n<li>Elektriska provningar<\/li>\n\n\n\n<li>Thermal or reliability testing<\/li>\n\n\n\n<li>Full-wafer pilot production<\/li>\n<\/ol>\n\n\n\n<p>Starting directly with a dense full-wafer pattern can increase development cost and make process problems more difficult to isolate.<\/p>\n\n\n\n<p>A test coupon can be used to evaluate:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Several via diameters<\/li>\n\n\n\n<li>Different via pitches<\/li>\n\n\n\n<li>Multiple taper angles<\/li>\n\n\n\n<li>Different metal thicknesses<\/li>\n\n\n\n<li>Sidewall coating versus full fill<\/li>\n\n\n\n<li>Resistance variation<\/li>\n\n\n\n<li>Termisk p\u00e5frestning<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">20. How to Evaluate a TGV Glass Wafer Supplier<\/h2>\n\n\n\n<p>A qualified supplier should be able to discuss the complete process, not only the minimum hole diameter.<\/p>\n\n\n\n<p>Evaluate the following areas:<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Material capability<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Available glass types<\/li>\n\n\n\n<li>Wafer diameters<\/li>\n\n\n\n<li>Thickness range<\/li>\n\n\n\n<li>Material certificates<\/li>\n\n\n\n<li>Traceability<\/li>\n\n\n\n<li>Custom glass sourcing<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Via capability<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Minimum and maximum via diameter<\/li>\n\n\n\n<li>Supported aspect ratio<\/li>\n\n\n\n<li>Pitch capability<\/li>\n\n\n\n<li>Taper control<\/li>\n\n\n\n<li>Position tolerance<\/li>\n\n\n\n<li>Sidewall-quality control<\/li>\n\n\n\n<li>Crack and chipping inspection<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Metallization capability<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Seed-layer deposition<\/li>\n\n\n\n<li>Adhesion and barrier layers<\/li>\n\n\n\n<li>Sidewall plating<\/li>\n\n\n\n<li>Partial or full filling<\/li>\n\n\n\n<li>Copper-planarization capability<\/li>\n\n\n\n<li>Surface metallization<\/li>\n\n\n\n<li>Redistribution layers<\/li>\n\n\n\n<li>Elektriska provningar<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Quality capability<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Dimensional metrology<\/li>\n\n\n\n<li>Cross-sectional inspection<\/li>\n\n\n\n<li>X-ray inspection<\/li>\n\n\n\n<li>Surface analysis<\/li>\n\n\n\n<li>Elektriska provningar<\/li>\n\n\n\n<li>Wafer mapping<\/li>\n\n\n\n<li>Process traceability<\/li>\n\n\n\n<li>Inspection reports<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Production capability<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Prototype service<\/li>\n\n\n\n<li>Pilot production<\/li>\n\n\n\n<li>Volume production<\/li>\n\n\n\n<li>Yield management<\/li>\n\n\n\n<li>Capacity planning<\/li>\n\n\n\n<li>Lead-time control<\/li>\n\n\n\n<li>Packaging and shipping<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Engineering support<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Design-for-manufacturing review<\/li>\n\n\n\n<li>Drawing review<\/li>\n\n\n\n<li>Material recommendation<\/li>\n\n\n\n<li>Via-structure recommendation<\/li>\n\n\n\n<li>Metallization support<\/li>\n\n\n\n<li>Reliability analysis<\/li>\n\n\n\n<li>Failure analysis<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">TGV Glass Wafer RFQ Checklist<\/h2>\n\n\n\n<p>An accurate RFQ should include the following information.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Glass substrate<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Glass type<\/li>\n\n\n\n<li>Material grade<\/li>\n\n\n\n<li>Wafer diameter<\/li>\n\n\n\n<li>Starting thickness<\/li>\n\n\n\n<li>Final thickness<\/li>\n\n\n\n<li>Total tjockleksvariation<\/li>\n\n\n\n<li>Bow and warp<\/li>\n\n\n\n<li>Surface roughness<\/li>\n\n\n\n<li>Edge profile<\/li>\n\n\n\n<li>Optical-transmission requirement<\/li>\n\n\n\n<li>Coefficient-of-thermal-expansion requirement<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Via dimensions<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Via diameter<\/li>\n\n\n\n<li>Top opening diameter<\/li>\n\n\n\n<li>Bottom opening diameter<\/li>\n\n\n\n<li>Minimum internal diameter<\/li>\n\n\n\n<li>Via depth<\/li>\n\n\n\n<li>Via aspect ratio<\/li>\n\n\n\n<li>Via taper angle<\/li>\n\n\n\n<li>Via pitch<\/li>\n\n\n\n<li>Via position tolerance<\/li>\n\n\n\n<li>Edge-to-via distance<\/li>\n\n\n\n<li>Total via count<\/li>\n\n\n\n<li>Via pattern drawing<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Via quality<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Maximum chipping<\/li>\n\n\n\n<li>Maximum crack length<\/li>\n\n\n\n<li>Sidewall roughness<\/li>\n\n\n\n<li>Debris requirement<\/li>\n\n\n\n<li>Heat-affected-zone limit<\/li>\n\n\n\n<li>Blocked-via acceptance<\/li>\n\n\n\n<li>Inspection method<\/li>\n\n\n\n<li>Sampling standard<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Metallisering<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Metal material<\/li>\n\n\n\n<li>Adhesion layer<\/li>\n\n\n\n<li>Barrier layer<\/li>\n\n\n\n<li>Seed layer<\/li>\n\n\n\n<li>Sidewall coating or full fill<\/li>\n\n\n\n<li>Required metal thickness<\/li>\n\n\n\n<li>Maximum void size<\/li>\n\n\n\n<li>Maximum via resistance<\/li>\n\n\n\n<li>Surface finish<\/li>\n\n\n\n<li>Top-side pad pattern<\/li>\n\n\n\n<li>Bottom-side pad pattern<\/li>\n\n\n\n<li>Redistribution-layer requirement<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Testing and quality documents<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Dimensional report<\/li>\n\n\n\n<li>Material certificate<\/li>\n\n\n\n<li>Wafer map<\/li>\n\n\n\n<li>Cross-sectional images<\/li>\n\n\n\n<li>Electrical test report<\/li>\n\n\n\n<li>Plating-thickness report<\/li>\n\n\n\n<li>Bow and warp report<\/li>\n\n\n\n<li>Reliability-test requirement<\/li>\n\n\n\n<li>Traceability requirement<\/li>\n\n\n\n<li>Packaging specification<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Commercial information<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Prototype quantity<\/li>\n\n\n\n<li>Pilot quantity<\/li>\n\n\n\n<li>Annual forecast<\/li>\n\n\n\n<li>Required delivery date<\/li>\n\n\n\n<li>Target unit price<\/li>\n\n\n\n<li>Incoterms<\/li>\n\n\n\n<li>Shipping destination<\/li>\n\n\n\n<li>Special packaging requirements<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Common RFQ Mistakes<\/h2>\n\n\n\n<p>Buyers should avoid submitting incomplete requirements such as:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>\u201cNeed 200 mm TGV wafer\u201d<\/li>\n\n\n\n<li>\u201cVia size is 50 \u03bcm\u201d<\/li>\n\n\n\n<li>\u201cNeed copper metallization\u201d<\/li>\n\n\n\n<li>\u201cPlease quote according to drawing\u201d when no cross-section is provided<\/li>\n<\/ul>\n\n\n\n<p>These requests do not define:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Glass composition<\/li>\n\n\n\n<li>Wafer thickness<\/li>\n\n\n\n<li>Top and bottom via diameter<\/li>\n\n\n\n<li>Via pitch<\/li>\n\n\n\n<li>Taper<\/li>\n\n\n\n<li>Metal thickness<\/li>\n\n\n\n<li>Sidewall coating or full filling<\/li>\n\n\n\n<li>Electrical resistance<\/li>\n\n\n\n<li>Quality acceptance criteria<\/li>\n<\/ul>\n\n\n\n<p>An incomplete RFQ usually produces a preliminary estimate rather than an accurate production quotation.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Vanliga fr\u00e5gor och svar<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">What glass is best for TGV wafers?<\/h3>\n\n\n\n<p>There is no universal best glass. The correct material depends on thermal expansion, dielectric properties, optical performance, processing temperature, mechanical strength and bonding requirements.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">What is the minimum TGV via diameter?<\/h3>\n\n\n\n<p>The minimum achievable diameter depends on the glass type, wafer thickness, aspect ratio, via pitch and formation method. Buyers should request demonstrated capability for their complete wafer design.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Can TGV holes be completely filled with copper?<\/h3>\n\n\n\n<p>Yes, some TGV structures use complete copper filling. However, the design must address plating voids, thermal stress, copper protrusion, wafer warpage and surface planarization.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Is a tapered TGV better than a straight TGV?<\/h3>\n\n\n\n<p>Neither profile is universally better. Tapered vias can simplify seed deposition and plating, while straight vias can support higher routing density. The correct choice depends on the process and electrical design.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">What information is required for a TGV quotation?<\/h3>\n\n\n\n<p>The supplier needs the glass type, wafer size, thickness, via diameter, via pitch, via count, via profile, position tolerance, metallization structure, testing requirement and order quantity.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Can a TGV supplier provide only drilled glass without metal?<\/h3>\n\n\n\n<p>Yes. Projects may purchase unmetalized TGV glass, seed-coated wafers, partially plated wafers or fully metallized interposers. The required process scope should be clearly stated.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">How is TGV via quality inspected?<\/h3>\n\n\n\n<p>Common methods include optical inspection, three-dimensional measurement, cross-sectional analysis, scanning electron microscopy, X-ray inspection and electrical testing.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">What causes voids in metal-filled TGVs?<\/h3>\n\n\n\n<p>Possible causes include incomplete seed coverage, restricted via geometry, poor cleaning, non-uniform current distribution, gas trapping and unsuitable plating conditions.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Why is a prototype run important?<\/h3>\n\n\n\n<p>A prototype run verifies via geometry, metallization continuity, resistance, wafer stress and reliability before the buyer commits to full-wafer or high-volume production.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Slutsats<\/h2>\n\n\n\n<p>Selecting a TGV glass wafer supplier requires a complete review of the glass substrate, via geometry, metallization structure and quality-control process.<\/p>\n\n\n\n<p>The most important purchasing parameters include:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Glass composition<\/li>\n\n\n\n<li>Wafer diameter and thickness<\/li>\n\n\n\n<li>Via diameter and aspect ratio<\/li>\n\n\n\n<li>Via pitch and pattern<\/li>\n\n\n\n<li>Sidewall quality<\/li>\n\n\n\n<li>Taper and position tolerance<\/li>\n\n\n\n<li>Metallization method<\/li>\n\n\n\n<li>Metal thickness and fill quality<\/li>\n\n\n\n<li>Electrical resistance<\/li>\n\n\n\n<li>Wafer bow and warp<\/li>\n\n\n\n<li>Inspection and reliability requirements<\/li>\n<\/ul>\n\n\n\n<p>A technically complete RFQ should include both a top-view layout and a via cross-section drawing.<\/p>\n\n\n\n<p>Send the supplier the glass material, wafer diameter, thickness, via dimensions, via pitch, metallization requirements, quantity and inspection standard for a manufacturability review and quotation.<\/p>","protected":false},"excerpt":{"rendered":"<p>Through-glass via, commonly abbreviated as TGV, is an important interconnection technology used in advanced packaging, radio-frequency devices, MEMS, sensors, optical systems and wafer-level integration. TGV glass wafers contain vertical holes or conductive vias extending through the glass substrate. These structures can provide electrical connection, signal routing, thermal paths or alignment features while maintaining the electrical [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":2628,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[24],"tags":[],"class_list":["post-2627","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-industry-news"],"_links":{"self":[{"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/posts\/2627","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/comments?post=2627"}],"version-history":[{"count":1,"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/posts\/2627\/revisions"}],"predecessor-version":[{"id":2629,"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/posts\/2627\/revisions\/2629"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/media\/2628"}],"wp:attachment":[{"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/media?parent=2627"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/categories?post=2627"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.zmsh-semitech.com\/sv\/wp-json\/wp\/v2\/tags?post=2627"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}